M16C6K9 Datasheet, PDF (156/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
LPC Bus Interface
LPC control register (LPCCON)
• LPC bus interface enable bit (LPCBEN)
“0”: P30 -P36 use as GPIO
“1”: P30 -P36 use as LPC bus interface
• LPC bus buffer 0 enable bit (LPCEN0)
“0”: LPC bus buffer0 disable
“1”: LPC bus buffer0 enable
• LPC bus buffer 1 enable bit (LPCEN1)
“0”: LPC bus buffer1 disable
“1”: LPC bus buffer1 enable
• LPC bus buffer 2 enable bit (LPCEN2)
“0”: LPC bus buffer2 disable
“1”: LPC bus buffer2 enable
• LPC bus buffer 3 enable bit (LPCEN3)
“0”: LPC bus buffer3 disable
“1”: LPC bus buffer3 enable
• LPC software reset bit (LPCSR)
______________
By setting the bit to “1”, LPC interface is reset by the same status as LRESET=“L”. After 1.5 cycles of
BCLK at writing “1”, reset is released and the bit becomes “0”.
Nothing happens if “0” is set.
• SYNC output selection bits (SYNCSEL0,SYNCSEL1)
The content of SYNC output can be selected by bit 0,1 (SYNC output selection bits) of LPC control register.
Fig.GF-6 shows the configuration of LPC control register, Table.GF-1 shows the content of SYNC output
selected by SYNC output selection bits.
Table GF-1 SYNC output
SYNCSEL1 SYNCSEL0
0
0
0
1
1
0
1
1
SYNC cycle
1
4
1
4
1st cycle
00002
01102
10102
01102
SYNC output
2nd cycle 3rd cycle
4th cycle
01102
01102
00002
01102
01102
10102
Rev.1.00 Jun 06, 2003 page 156 of 290