M16C6K9 Datasheet, PDF (202/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
MULTI-MASTER I²C-BUS Interface
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in Fig.GC-19, GC-20 and Table.GC-11 The
START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be de-
tected only when the input signal of the SCL and SDA pins satisfy with three conditions: SCL release time, setup
time, and hold time (see Table.GC-11). The BB flag is set to “1” by detecting the START condition and is reset
to “0” by detecting the STOP condition. The BB flag set/reset timing is different in the standard clock mode and
the high-speed clock mode. Refer to Table GC-11, the BB flag set/reset time.
SCL
SDA
BB flag
SCL release time
Setup
time
Hold
time
BB flag
set time
Fig.GC-19 Start condition detection timing diagram
SCL
SDA
BB flag
SCL release time
Setup
time
Hold
time
BB flag
reset time
Fig.GC-20 Stop condition detection timing diagram
Table.GC-11 Start/Stop generation timing table
Standard clock mode
SCL release time
SSC value + 1 cycle (6.25µs)
Setup time
SSC value + 1 cycle < 4.0µs (3.25µs)
2
Hold time
SSC value cycle < 4.0µs (3.0µs)
2
BB flag set/reset
SSC value - 1 +2 cycle (3.375µs)
time
2
High-speed clock mode
4 cycle (1.0µs)
2 cycle (0.5µs)
2 cycle (0.5µs)
3.5 cycle (0.875µs)
Note: Unit : Cycle number of system clock VIIC
SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0.
Do not set “0” or an odd number to SSC value. The value in parentheses is an example when the
I²C START/STOP condition control register is set to “1816” at VIIC = 4 MHz.
Rev.1.00 Jun 06, 2003 page 202 of 290