M16C6K9 Datasheet, PDF (52/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Interrupt
Time (a) is dependent on the instruction under execution. 30 cycles is the maximum required for the DIVX
instruction (without wait).
Time (b) is as shown in Table.DD-5
Table.DD-5 Time required for executing the interrupt sequence
Interrupt vector address Stack pointer (SP) value 16-Bit bus, without wait
Even
Even
18 cycles (Note 1)
8-Bit bus, without wait
20 cycles (Note 1)
Even
Odd
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Even
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Odd
20 cycles (Note 1)
20 cycles (Note 1)
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
BCLK
Address bus
Data bus
R
W
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
Address
0000
Interrupt
information
Indeterminate
Indeterminate
Indeterminate
SP-2
SP-4
vec
vec+2
PC
SP-2
SP-4
vec
vec+2
contents contents contents contents
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Fig.DD-6 Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in
Table.DD-6 is set in the IPL.
Table.DD-6 Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels
_______
Watchdog timer, NMI
Value set in the IPL
7
Reset
0
Other
Not changed
Rev.1.00 Jun 06, 2003 page 52 of 290