M16C6K9 Datasheet, PDF (164/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
LPC Bus Interface
GateA20 output function
The GateA20 pin (port P42) can be controlled by LPC interface function channel 0 in hardware.
Hardware GateA20 is sharing with P42 pin. Setting “1” to bit 0 of GateA20 control register enables the hard-
ware GateA20 function. The default value of hardware GateA20 is “1”.
The GateA20 control register is shown in Fig.GF-9.
When the host CPU writes “D1” command to address 006416, and then writes data to address 006016 in
succession, the value of bit 1 of the data will be output to GateA20 pin. The timing is shown in Fig.GF-10.
The GateA20 operation sequences are shown in Fig.GF-11, Fig.GF-12. As shown in the figures, there is no
change in input buffer full flag(IBF0) and no input buffer full(IBF) interrupt request, but the input data bus
buffer and XA2 flag are changed in these sequences.
The value of the GateA20 output pin will be held till the data next to D1 command is written in. P42 becomes
_____________
I/O port and the the value of GateA20 becomes "0" when LRESET input is “L”. GateA20 will be initialized even
if the sequence is executed. However, the GateA20 enable bit will not be changed and GateA20 output pin
_____________
will be resumed after the LRESET input becomes “H”.
GateA20 control register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
GA20CON
Address
002CA16
Bit Symbol
Bit name
GA20EN GateA20 enable bit
Reserved bit
Reset
0016
Function
RW
0 : P42 as GPIO
1 : Hardware GateA20 function enable
Must be set to “0”
Nothing is assigned.
Meaningless in writing. "0" in reading.
Fig.GF-9 GateA20 control register
LCLK
START WRITE
16-bit address
DATA
TAR
SYNC
TAR
LFRAME
LAD (3:0)
GateA20 pin
Previous value
The value of bit 1 of the data
Fig.GF-10 GateA20 output timing
Rev.1.00 Jun 06, 2003 page 164 of 290