M16C6K9 Datasheet, PDF (192/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
MULTI-MASTER I²C-BUS Interface
•Bits 2,3 : Port function selection bits PED, PEC
When ES0 bit of I²C control register 0 is set to “1”, P61/P63 and P60/P62 function as SCL and SDA respec-
tively. However, if PED is set to “1”, SDA functions as output port so as to SCL if PEC is set to “1”. In this case,
if “0” or “1” is written to the port register, the data can be output on to the I²C-BUS regardless of the internal
SCL/SDA output signals. The functions of SCL/SDA are returned back by setting PED/PEC to “1” again.
If the ports are set in input mode, the values on the I²C-BUS can be known by reading the port register
regardless of the values of PED and PEC.Table GC-4 shows the port specification.
Table.GC-4 Ports specifications
Pin name
ES0 bit
P60/P62
0
1
1
P61/P63
ES0 bit
0
1
1
PED bit
-
0
1
PEC bit
-
0
1
P6 port
direction register
0/1
-
-
P6 port
direction register
0/1
-
-
Function
Port I/O function
SDA I/O function
SDA input function, port output function
Function
Port I/O function
SCL I/O function
SCL input function, port output function
•Bits 4,5 : SDA/SCL logic output value monitor bits SDAM /SCLM
It is possible to monitor the logic value of the SDA and SCL output signals from I²C-BUS interface circuit.
SDAM can monitor the output logic value of SDA. SCLM can monitor the output logic value of SCL. The bits are
read-only. Write “0” if in writing (Writing “1” is reserved)
•Bits 6,7 : I²C system clock selection bits ICK0, ICK1
These bits select the basic operation clock of I²C-BUS interface circuit. It is possible to select I²C system
clock VIIC among 1/2,1/4 and 1/8 of main clock f(XIN) and 1/2 of external I²C clock (ICCK)
Table.GC-5 I²C system clock selecting bits
ICK1
ICK0
I²C system clock
0
0
VIIC = 1 / 2f1
0
1
VIIC = 1 / 4f1
1
0
VIIC = 1 / 8f1
1
1
VIIC = 1 / 2ICCK
Note: f1 = f(XIN)
ICCK = External I²C clock
Rev.1.00 Jun 06, 2003 page 192 of 290