M16C6K9 Datasheet, PDF (66/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Interrupt
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets the request bit, which the interrupt source is enabled with the
highest priority, to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Hence do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer is initialized to 000016 right after the reset. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the
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stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the
beginning of a program. Concerning the first instruction immediately after reset, generating any interrupts
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including the NMI interrupt is prohibited.
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(3) The NMI interrupt
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• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistor (pull-
up) if unused. Be sure to work on it.
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• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
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when the NMI interrupt is input.
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• Do not reset the CPU with the input to the NMI pin being in the “L” state.
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• Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to the
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NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned down.
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• Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to the
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NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved. In this
instance, the CPU is returned to the normal state by a later interrupt.
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• Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU.
(4) External interrupt
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• Either an “L” level or an “H” level of at least 380 ns width is necessary for the signal input to pins INT0
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through INT11 regardless of the CPU operation clock.
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• When the polarity of the INT0 to INT11 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Fig.DD-21 shows the procedure for changing
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the INT interrupt generate factor.
Rev.1.00 Jun 06, 2003 page 66 of 290