M16C6K9 Datasheet, PDF (262/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
CPU Reprogram Mode
Feature Outline (CPU reprogram mode)
In CPU reprogram mode, the CPU erases, programs and reads the on-chip flash memory as instructed by
S/W commands. The reprogram control program must be transferred to the RAM area before it can be
executed.
The CPU reprogram mode is accessed by writing “1” to the CPU reprogram select bit (bit 1 in address
03B716). S/W commands are accepted once the mode is accessed.
In CPU reprogram mode, the writing and reading of the commands and data should be in even address (“0”
for byte address A0) in 16-bit unit, so the 8-bit unit S/W commands should be written in even address.
Commands are ignored with odd address.
Use S/W commands to control flash memory programming and erasing. Whether the programming and
erasing operation terminates correctly or in error can be verified by reading the status register.
Fig.BB-1 shows the flash control register.
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Bit 0 is the RY/BY status flag exclusively used to read the operating status of the flash memory. During
programming and erasing operation, it is “0”, otherwise it is “1”.
Bit 1 is the CPU reprogram mode select bit. When the bit is set to “1”, CPU reprogram mode is entered S/W
commands then can be accessed. In CPU reprogram mode, the CPU cannot access the on-chip flash memory
directly. Therefore, use the control program in RAM to write the bit to “1”. To set the bit, it is necessary to write
“0” and then write “1” in succession. The bit can be cleared to “0” by only writing the “0”.
Bit 3 is the flash memory reset bit used to reset the control circuit of the on-chip flash memory. The bit is used
when exiting the CPU reprogram mode and when flash memory access has failed. When the CPU reprogram
mode select bit is “1”, writing “1” to the bit resets the control circuit. To release the reset, it is necessary to set
the bit to “0”. If the control circuit is reset while erasing is in progress, the wait for 5 ms is needed so that the
flash memory can restore to the normal operation.
Bit 5 of the flash control register 0 is the user ROM select bit. It is enabled only in boot mode. When the bit is
set to “1”, the accessed area is switched from boot ROM to user ROM. When CPU reprogram mode is
entered in boot mode, please set this bit to “1”. The bit is disabled when program starts in user ROM. Please
write the bit with the program that is not located in on-chip flash memory area.
Fig.BB-2 shows a flowchart for the setting/ releasing the CPU reprogram mode.
Rev.1.00 Jun 06, 2003 page 262 of 290