M16C6K9 Datasheet, PDF (120/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Clock asynchronous serial I/O (UART) mode
(c) Function for switching serial data logic (UART2)
When the data logic selection bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the
transmission buffer register or reading the reception buffer register. Fig.GA-20 shows the example of timing
for switching serial data logic.
• When LSB first, parity enabled, one stop bit
Transfer clock ^{“H”}
“L”
TxD2 ^{“H”}
(no reverse) _{“L”}
TxD2 ^{“H”}
(reverse) _{“L”}
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST : Start bit
P : Even parity
SP : Stop bit
Fig.GA-20 Timing for switching serial data logic
(d) TxD, RxD I/O polarity switching function (UART2)
This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for usual
use.
(e) Bus collision detection function (UART2)
This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising edge
of the transfer clock; if their values are different, then an interrupt request occurs. Fig.GA-21 shows the
example of detection timing of a bus collision (in UART mode).
Transfer clock ^{“H”}
“L”
TxD2 ^{“H”}
ST
“L”
RxD2 ^{“H”}
ST
“L”
Bus collision detection _{“1”}
interrupt request signal _{“0”}
Bus collision detection _{“1”}
interrupt request bit
“0”
Fig.GA-21 Detection timing of a bus collision (in UART mode)
Rev.1.00 Jun 06, 2003 page 120 of 290
SP
SP
ST : Start bit
SP : Stop bit