M16C6K9 Datasheet, PDF (180/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
MULTI-MASTER I²C-BUS Interface
I²C Data Shift Register
The I²C data shift register (address 032016, 033016, 031016) is an 8-bit shift register to store receiving data
and write transmission data. When transmit data is written into this register, it is transferred to the outside
from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register
are shifted by one bit to the left. When data is received, it is input to this register from bit 0 in synchronization
with the SCL clock, and each time one-bit data is input, the data of this register are shifted by one bit to the
left. The timing of storing received data to this register is shown in figure GC-3.The I²C data shift register is
in a write enable status only when the I²C-BUS interface enable bit (ES0 bit : bit 3 of address 032316,
033316, 031316) of the I²C control register 0 is “1”. The bit counter is reset by a write instruction to the I²C
data shift register. When both the ES0 bit and the MST bit of the I²C status register (address 032816, 033816,
031816) are “1”, the SCL is output by a write instruction to the I²C data shift register. Reading data from the
I²C data shift register is always enabled regardless of the value of ES0 bit.
I²C data shift register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S0i(i=0,1,2)
Address
032016,033016,031016
When reset
--
Function
RW
Transmission data /receiving data are stored.
In the master transmission mode, the start condition/ stop condition are
triggered by writing data to the register (refer to the section on the method to
generate the start/stop condition). The transmission/receiving are started
synchronized with SCL.
Note
Note The write is only enabled when bus interface enable bit (ES0 bit) is "1".
Because the register is used both for storing transmission data/receiving data, the
transmission data should be written after the receiving data are read out before
writing transmission data to this register.
Fig.GC-2 I²C data shift register
SCL
SDA
Internal SCL
Internal SDA
Shift clock
tdfil
tdfil
tdsft
tdfil : Noise elimination circuit delay time
1 to 2 VIIC cycle
tdsf : Shift clock delay time
1 VIIC cycle
Storing data at shift clock rising edge.
Fig.GC-3 The timing of receiving data stored to I²C data shift register
Rev.1.00 Jun 06, 2003 page 180 of 290