M16C6K9 Datasheet, PDF (158/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
LPC Bus Interface
Basic operation of LPC bus interface
The status transition of LPC bus interface is shown in Figure GF-7.
Setting steps for using LPC bus interface is explained below.
• Setting bit3 (LPC interface enable bit) of LPC control register ( address 02D616 ) to "1"
• Choosing which LPC bus buffer channel will be used
• Setting "1" to bits 4-7 (LPC bus buffer 0-3 enable bit) of LPC control register ( address 02D616 ).
• The 16-bit slave address of LPC bus buffer channel is defined by writing 16-bit slave address to LPC 1-3
address registers ( address 02D016 to 02D516 ). If channel 1-3 LPC bus buffer is chosen, set the address to
the corresponding address register.
• Selecting IBF/ OBE interrupt in data bus buffer control register0 ( address 02C816 )
• Selecting OBF output port in data bus buffer control register1 ( address 02C916 )
<1> Example of I/O writing cycle from HOST
Writing timing is shown in Figure GF-8.
The basic communication cycles of LPC I/O protocol are 13 cycles. The data of LAD[3:0] will be read by the
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rising edge of LCLK. Communication will start from LFRAME falling edge.
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• 1^st cycle : When LFRAME is "Low", sending "00002 " to LAD[3:0] for communication start frame detecting.
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• 2^nd cycle : When LFRAME is "High", sending "001X2 " to LAD[3:0] for write frame detecting.
• From 3^rd cycle to 6^th cycle: These four cycles are detecting for 16 bits slave address.
3^rd cycle: The slave address which is from host is written to slave address register [15:12] through LAD[3:0]
4^th cycle: The slave address which is from host is written to slave address register [11:8] through LAD[3:0]
5^th cycle: The slave address which is from host is written to slave address register [7:4] through LAD[3:0]
6^th cycle: The slave address which is from host is written to slave address register [3:0] through LAD[3:0]
• 7^th and 8^th cycles are used for one data byte transfer.
7^th cycle: The data which is from host is written to input data buffer[3:0] through LAD[3:0]
8^th cycle: The data which is from host is written to input data buffer[7:4] through LAD[3:0]
• 9^th and 10^thcycles are for changing the communication direction from host→slave to slave→host
9^th cycle: Host outputs "11112 " to LAD[3:0]
10^thcycle: The LAD[3:0] will be set to Hi-Z by HOST to switch the communication direction.
• 11^th cycle: The "00002 " (SYNC OK) is output to LAD[3:0] for acknowledge.
• 12^th cycle: The "11112 " is output to LAD[3:0]. The XA2 and IBF flag are set. IBF interrupt signal is generated.
• 13^th cycle: The LAD[3:0] will be set to Hi-Z by slave to switch the communication direction.
During the host write period, the bit2 (A2) status of 16 bits slave address will be latched to XA2 flag. When 8
bits data from input data buffer are read out by slave CPU, the IBF flag will be cleared simultaneously.
Rev.1.00 Jun 06, 2003 page 158 of 290