M16C6K9 Datasheet, PDF (105/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Serial I/O
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
When reset
X00000002
Bit
symbol
U0IRS
Bit name
UART0 transmit interrupt
factor selection bit
Function
(During clock synchronous
serial I/O mode)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Function
(During UART mode)
RW
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS UART1 transmit interrupt 0 : Transmit buffer empty (Tl = 1)
factor selection bit
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0RRM UART0 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
CLKMD0 CLK/CLKS selection bit 0 Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
Invalid
CLKMD1 CLK/CLKS selection bit 1
(Note)
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
Must always be “0”
RCSP Separate CTS/RTS bit
0 : CTS/RTS shared pin
1 : CTS/RTS separated
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock selection bit (bit 3 at address 03A816) = “0”.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00 00
Symbol
U2SMR
Address
037716
When reset
0016
Bit
symbol
Bit name
Reserved bits
Function
(During clock synchronous
serial I/O mode)
Must always be “0”
Function
(During UART mode)
RW
ABSCS ^{Bus collision detect}
sampling
clock selection bit
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ACSE
Auto clear function
selection bit of
transmit enable bit
SSS
Transmit start condition
selection bit
Must always be “0”
Must always be “0”
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
0 : Ordinary
1 : Falling edge of RxD2
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
Fig.GA-8 Serial I/O-related registers (5)
Rev.1.00 Jun 06, 2003 page 105 of 290