M16C6K9 Datasheet, PDF (205/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
MULTI-MASTER I²C-BUS Interface
Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the
ACK return mode is shown below.
1)Set a slave address in the high-order 7 bits of the I²C address register and “0” into the RBW bit.
2)Set the ACK return mode and SCL = 100 kHz by setting “0016” in the I²C control register 1 and “8516” in the
I²C clock control register respectively. (f(XIN)=8MHz)
3)Set “0016” in the I²C status register so that transmission/reception mode is initialized.
4)Set a communication enable status by setting “0816” in the I²C control register 0.
5)Confirm the bus free condition by the BB flag of the I²C status register.
6)Set “E016” in the I²C status register to setup a standby of START condition.
7)Set the destination address data for transmission in high-order 7 bit of I²C data shift register and set “0” in
the least significant bit. And then a START condition occurs. At this time, SCL for 1 byte and an ACK clock
automatically generate.
8)Set transmission data in the I²C data shift register. At this time, an SCL and an ACK clock automatically
generate.
9)When transmitting control data of more than 1 byte, repeat step 8).
10)Set “C016” in the I²C status register to setup a STOP condition if ACK is not returned from slave reception
side or transmission ends.
11)A STOP condition occurs when writing dummy data to I²C data shift register.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK
return mode and using the addressing format is shown below.
1)Set a slave address in the high-order 7 bits of the I²C address register and “0” in the RBW bit.
2)Set the ACK clock mode and SCL = 400 kHz by setting “0016” in the I²C control register 1 and “A516” in the
I²C clock control register respectively. (f(XIN)=8MHz)
3)Set “0016” in the I²C status register so that transmission/reception mode is initialized.
4)Set a communication enable status by setting “0816” in the I²C control register 0.
5)When a START condition is received, an address comparison is performed.
6)•When all transmitted addresses are “0” (general call):
AD0 of the I²C status register is set to “1” and an interrupt request signal occurs.
•When the transmitted addresses agree with the address set in1):
ASS of the I²C status register is set to “1” and an interrupt request signal occurs.
•In the cases other than the above AD0 and AAS of the I²C status register are set to “0” and no interrupt
request signal occurs.
7)Set dummy data in the I²C data shift register.
8)After receiving 1 byte data, it returns an ACK automatically and an interrupt request signal occurs.
9)In the case of whether returning an ACK or not by the content of the received control data, set the WIT bit of
I²C control register 1 to “1”, and after writing dummy data to I²C data shift register, receives the control data.
10)After receiving 1 byte data, an interrupt request signal occurs, set the ACKBIT to “1” or “0” by reading the
content of the data shift register, and then returns or does not return an ACK.
11)When receiving control data of more than 1 byte, repeat step 7) 8) or 7) 10).
12)When a STOP condition is detected, the communication ends.
Rev.1.00 Jun 06, 2003 page 205 of 290