M16C6K9 Datasheet, PDF (78/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
DMAC
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on the same sampling cycle (a sampling cycle means one period from
the rising edge to the falling edge of BCLK), the DMA request bits of applicable channels concurrently turn to
"1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer. When
DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus access,
then DMA1 starts data transfer and gives the bus right to the CPU.
An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer request
signals due to external factors concurrently occur.
Fig.EC-6 An example of DMA transfer effected by external factors.
An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.
BCLK
DMA0
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Fig.EC-6 An example of DMA transfer effected by external factors
Obtaining
the bus
right
Rev.1.00 Jun 06, 2003 page 78 of 290