M16C6K9 Datasheet, PDF (210/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
PS2 Interface
The PS2 interface performs 1 byte data transfer with the format shown in Fig.GK-2.
Table GK-1 shows the communication specification.
Table GK-1 Communication specification
Item
Specification
Data transfer format
*Start bit
: 1 bit
*Data bit
: 8 bits (LSB first)
*Parity bit
: 1 bit (Odd)
*Stop bit
: 1 bit
*Acknowledge : 1 bit (Transmission only)
Transfer clock
*Using the clock, which is synchronized with the sampling clock of PS2
clock (CLK)
Reception start condition
*The following conditions should be met for reception start
1) Setting reception enable bit to “1”
2) The detection of “L” on both PS2 clock (CLK) and PS2 data (DAT) lines
Transmission start condition *The following conditions should be met for transmission start
1) Setting transmission data to PS2i shift register
2) Setting transmission enable bit to “1”
Transfer abort
*The following conditions should be met for transfer abort
1) Setting transfer interruption bit to “1”
2) The transfer completion flag becomes “1”
Interrupt request generation
*In reception: At the completion of stop bit reception
timing
*In transmission: At the completion of ACK bit reception.
*In transfer interruption: At the completion of transfer interruption
Error detection
*Parity error (In reception)
It occurs when there is a parity error in data reception
*Framing error (In reception)
It occurs when the detection of stop bit of reception data fails.
*Abnormal acknowledge reception (In transmission)
It occurs when NAK is received from a device side after the data
transmission
Selection function
*Sampling clock selection
Selecting the clock which samples the PS2 clock (CLK) and PS2 data (DAT)
Rev.1.00 Jun 06, 2003 page 210 of 290