M16C6K9 Datasheet, PDF (207/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
MULTI-MASTER I²C-BUS Interface
SCL
SDA
BB flag
Bit reset signal
Related bits
RBW
MST
TRX
1.5VIIC cycle
Fig.GC-22 The timing of bit reset (The detection of STOP condition)
SCL
SDA
BB flag
Bit reset signal
Related bits
BC0 - BC2
TRX(slave mode)
Fig.GC-23 The timing of bit reset (The detection of START condition)
SCL
PIN bit
Bit reset signal
Bit set signal
2VIIC cycle
1VIIC cycle
The bits referring
to reset
BC0 - BC2
MST(When in arbitration lost)
TRX(When in NACK reception in slave
transmission mode)
The bits referring _{TRX(ALS="0" meanwhile the slave}
to set _{reception R/W bit = "1"}
Fig.GC-24 Bit set/reset timing ( at the completion of data transfer)
Rev.1.00 Jun 06, 2003 page 207 of 290