M16C6K9 Datasheet, PDF (149/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
LPC Bus Interface
LPC Bus Interface
LPC bus interface is based on Intel Low Pin Count (LPC) Interface Specification, Revision 1.0. It is I/O cycle
data transfer format of serial communication. 4 channels are built in. The function of data bus buffer and data
bus buffer status are almost the same as that of MELPS8-41 series. It can be written in or read out (as slave
mode) by the control signals from host CPU side. The LPC bus interface functionality block diagram is shown
in Figure GF-2. LPC data bus buffer functional Input / Output ports (P30-P36 ) are shared with GPIO port.
The setting of bit3 (LPC bus buffer enable bit) of LPC control register ( address 02D616 ) is as below:
0: General purpose Input / Output port
1: LPC bus buffer functional Input / Output port
The enabling of channel of LPC bus buffer is controlled by bits 4-7 (LPC bus buffer 0-3 enable bits) of LPC
control register (address 02D616 ). The slave address (16 bits) of LPC bus buffer channel 0 is fixed on 0060h,
0064h. The slave addresses (16 bits) of LPC bus buffer channel 1-3 are definable by setting LPC 1-3 ad-
dress register H, L (address 02D016 to 02D516 ). The setting value of bit2 of LPC1-3 address register (A2) L
will not be decoded. The bit is “0” when read from slave CPU. The A2 status of slave address is latched to
XA2 flag when written by host CPU. The input buffer full interrupt is generated when written in the data by
host CPU. The Output buffer empty interrupt is generated when read out the data by host CPU. As shown in
GF-1, the input buffer full interrupt request and output buffer empty interrupt request are switched by bit6, 7
of data bus buffer control register0.
Rev.1.00 Jun 06, 2003 page 149 of 290