M16C6K9 Datasheet, PDF (28/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Bus control
Bus control
(1) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) .
A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode
register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle
is executed in 2 BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”.
Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency)
of the electric characteristics.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits.
Table.EF-1 shows the software wait and bus cycles. Fig.EF-1 shows example bus timing when using soft-
ware waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table.EF-1 Software waits and bus cycles
Area
Wait bit
SFR
Internal
ROM/RAM
Invalid
0
1
Bus cycle
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
Rev.1.00 Jun 06, 2003 page 28 of 290