M16C6K9 Datasheet, PDF (75/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
DMAC
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source
read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The
number of read and write bus cycles depends on the source and destination addresses.
* Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source and
destination both start at even addresses.
Fig.EC-5 shows the example of the transfer cycles for a source read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the
destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle
changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to
both the destination write cycle and the source read cycle.
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table.EC-2 shows the num-
ber of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table.EC-2 No. of DMAC transfer cycles
Transfer unit
Bus width Access address
8-bit transfers
(DMBIT= “1”)
16-bit transfers
(DMBIT= “0”)
16-bit
(BYTE= “L”)
16-bit
(BYTE= “L”)
Even
Odd
Even
Odd
Single-chip mode
No. of read No. of write
cycles
cycles
1
1
1
1
1
1
2
2
Coefficient j, k
Internal memory
Internal ROM/RAM Internal ROM/RAM
No wait
With wait
1
2
SFR area
2
Rev.1.00 Jun 06, 2003 page 75 of 290