M16C6K9 Datasheet, PDF (125/292 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M16C/6K9 Group
Clock asynchronous serial I/O (UART) mode
UART2 Special Mode Register
The UART2 special mode register (address 037716) is used to control UART2 in various ways.
Fig.GA-26 shows the UART2 special mode register.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
0 00 0
Symbol
U2SMR
Address
037716
When reset
0016
Bit
symbol
Bit name
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
RW
Reserved bits
Must always be “0”
ABSCS ^{Bus collision detect}
sampling clock selection
bit
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ACSE
SSS
Auto clear function
selection bit of
transmit enable bit
Transmit start condition
selection bit
Must always be “0”
Must always be “0”
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
0 : Ordinary
1 : Falling edge of RxD2
Reserved bit
Must always be “0”
Fig.GA-26 UART2 special mode register
Some other functions added are explained here. Fig.GA-27 shows their workings.
Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock selection bit. The
bus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the nonconfor-
mity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”. If this
bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer A0 rather than at the rising
edge of the transfer clock.
Bit 5 of the UART2 special mode register is used as the auto clear function selection bit of transmit enable bit.
Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus collision
detect interrupt request bit (nonconformity).
Bit 6 of the UART2 special mode register is used as the transmit start condition selection bit. Setting this bit
to “1” starts the TxD transmission in synchronization with the falling edge of the RxD pin.
Rev.1.00 Jun 06, 2003 page 125 of 290