MC68HC908GR16 Datasheet, PDF (93/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Arithmetic/Logic Unit (ALU)
NOTE:
automatically after the CPU registers are saved on the stack, but before the
interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
To maintain M6805 Family compatibility, the upper byte of the index register (H) is
not stacked automatically. If the interrupt service routine modifies H, then the user
must stack and unstack H using the PSHH and PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack
and restores the interrupt mask from the stack. After any reset, the interrupt
mask is set and can be cleared only by the clear interrupt mask software
instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic operation,
or data manipulation produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or
data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a
carry out of bit 7 of the accumulator or when a subtraction operation requires a
borrow. Some instructions — such as bit test and branch, shift, and rotate —
also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
7.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction
set.
Refer to the CPU08 Reference Manual (Motorola document order number
CPU08RM/AD) for a description of the instructions and addressing modes and
more detail about the architecture of the CPU.
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Central Processor Unit (CPU)
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Data Sheet
93