MC68HC908GR16 Datasheet, PDF (52/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
3.4 Monotonicity
The conversion process is monotonic and has no missing codes.
3.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU interrupts
after each ADC conversion. A CPU interrupt is generated if the COCO bit is at
logic 0. The COCO bit is not used as a conversion complete flag when interrupts
are enabled.
3.6 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low power- consumption
standby modes.
3.6.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt
request from the ADC can bring the MCU out of wait mode. If the ADC is not
required to bring the MCU out of wait mode, power down the ADC by setting
ADCH4–ADCH0 bits in the ADC status and control register before executing the
WAIT instruction.
3.6.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending
conversion is aborted. ADC conversions resume when the MCU exits stop mode
after an external interrupt. Allow one conversion cycle to stabilize the analog
circuitry.
3.7 I/O Signals
The ADC module has eight pins shared with port B, PTB7/AD7–PTB0/AD0.
3.7.1 ADC Analog Power Pin (V_DDAD)
The ADC analog portion uses V_DDAD as its power pin. Connect the V_DDAD pin to
the same voltage potential as V_DD. External filtering may be necessary to ensure
clean V_DDAD for good results.
NOTE: For maximum noise immunity, route V_DDAD carefully and place bypass capacitors
as close as possible to the package.
V_DDAD and V_REFH are double-bonded on the MC68HC908GR16.
Data Sheet
52
Analog-to-Digital Converter (ADC)
For More Information On This Product,
Go to: www.freescale.com
MC68HC908GR16 — Rev. 1.0
MOTOROLA