MC68HC908GR16 Datasheet, PDF (154/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
13.3.2.7 Serial Peripheral Interface (SPI)
SPI CPU interrupt sources:
• SPI receiver full bit (SPRF) — The SPRF bit is set every time a byte
transfers from the shift register to the receive data register. The SPI receiver
interrupt enable bit, SPRIE, enables SPRF CPU interrupt requests. SPRF is
in the SPI status and control register and SPRIE is in the SPI control
register.
• SPI transmitter empty (SPTE) — The SPTE bit is set every time a byte
transfers from the transmit data register to the shift register. The SPI
transmit interrupt enable bit, SPTIE, enables SPTE CPU interrupt requests.
SPTE is in the SPI status and control register and SPTIE is in the SPI control
register.
• Mode fault bit (MODF) — The MODF bit is set in a slave SPI if the SS pin
goes high during a transmission with the mode fault enable bit (MODFEN)
set. In a master SPI, the MODF bit is set if the SS pin goes low at any time
with the MODFEN bit set. The error interrupt enable bit, ERRIE, enables
MODF CPU interrupt requests. MODF, MODFEN, and ERRIE are in the SPI
status and control register.
• Overflow bit (OVRF) — The OVRF bit is set if software does not read the
byte in the receive data register before the next full byte enters the shift
register. The error interrupt enable bit, ERRIE, enables OVRF CPU interrupt
requests. OVRF and ERRIE are in the SPI status and control register.
13.3.2.8 Serial Communications Interface (SCI)
SCI CPU interrupt sources:
• SCI transmitter empty bit (SCTE) — SCTE is set when the SCI data register
transfers a character to the transmit shift register. The SCI transmit interrupt
enable bit, SCTIE, enables transmitter CPU interrupt requests. SCTE is in
SCI status register 1. SCTIE is in SCI control register 2.
• Transmission complete bit (TC) — TC is set when the transmit shift register
and the SCI data register are empty and no break or idle character has been
generated. The transmission complete interrupt enable bit, TCIE, enables
transmitter CPU interrupt requests. TC is in SCI status register 1. TCIE is in
SCI control register 2.
• SCI receiver full bit (SCRF) — SCRF is set when the receive shift register
transfers a character to the SCI data register. The SCI receive interrupt
enable bit, SCRIE, enables receiver CPU interrupts. SCRF is in SCI status
register 1. SCRIE is in SCI control register 2.
• Idle input bit (IDLE) — IDLE is set when 10 or 11 consecutive logic 1s shift
in from the RxD pin. The idle line interrupt enable bit, ILIE, enables IDLE
CPU interrupt requests. IDLE is in SCI status register 1. ILIE is in SCI control
register 2.
Data Sheet
154
Resets and Interrupts
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MC68HC908GR16 — Rev. 1.0
MOTOROLA