MC68HC908GR16 Datasheet, PDF (73/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
CGM Registers
Table 4-2. PRE1 and PRE0 Programming
PRE1 and PRE0
00
01
10
11
P
Prescaler Multiplier
0
1
1
2
2
4
3
8
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range multiplier
E that, in conjunction with L (See 4.3.3 PLL Circuits, 4.3.6 Programming the
PLL, and 4.5.5 PLL VCO Range Select Register.) controls the hardware
center-of-range frequency, f_VRS. VPR1:VPR0 cannot be written when the
PLLON bit is set. Reset clears these bits.
Table 4-3. VPR1 and VPR0 Programming
VPR1 and VPR0
00
01
10
11
E
VCO Power-of-Two
Range Multiplier
0
1
1
2
2
4
3⁽¹⁾
8
1. Do not program E to a value of 3.
4.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking mode
Address: $0037
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LOCK
0
0
0
0
AUTO
ACQ
R
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 4-5. PLL Bandwidth Control Register (PBWC)
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Clock Generator Module (CGM)
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Data Sheet
73