MC68HC908GR16 Datasheet, PDF (153/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
Interrupts
13.3.2.2 Break Interrupt
The break module causes the CPU to execute an SWI instruction at a
software-programmable break point.
13.3.2.3 IRQ Pin
A logic 0 on the IRQ pin latches an external interrupt request.
13.3.2.4 Clock Generator (CGM)
The CGM can generate a CPU interrupt request every time the phase-locked loop
circuit (PLL) enters or leaves the locked state. When the LOCK bit changes state,
the PLL flag (PLLF) is set. The PLL interrupt enable bit (PLLIE) enables PLLF CPU
interrupt requests. LOCK is in the PLL bandwidth control register. PLLF is in the
PLL control register.
13.3.2.5 Timer Interface Module 1 (TIM1)
TIM1 CPU interrupt sources:
• TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1 counter value
rolls over to $0000 after matching the value in the TIM1 counter modulo
registers. The TIM1 overflow interrupt enable bit, TOIE, enables TIM1
overflow CPU interrupt requests. TOF and TOIE are in the TIM1 status and
control register.
• TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an input
capture or output compare occurs on channel x. The channel x interrupt
enable bit, CHxIE, enables channel x TIM1 CPU interrupt requests. CHxF
and CHxIE are in the TIM1 channel x status and control register.
13.3.2.6 Timer Interface Module 2 (TIM2)
TIM2 CPU interrupt sources:
• TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter value
rolls over to $0000 after matching the value in the TIM2 counter modulo
registers. The TIM2 overflow interrupt enable bit, TOIE, enables TIM2
overflow CPU interrupt requests. TOF and TOIE are in the TIM2 status and
control register.
• TIM2 channel flags (CH1F–CH0F) — The CHxF bit is set when an input
capture or output compare occurs on channel x. The channel x interrupt
enable bit, CHxIE, enables channel x TIM2 CPU interrupt requests. CHxF
and CHxIE are in the TIM2 channel x status and control register.
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Resets and Interrupts
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Data Sheet
153