MC68HC908GR16 Datasheet, PDF (235/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI) Module
I/O Registers
Address: $0010
Bit 7
Read:
SPRIE
Write:
Reset:
0
R
6
5
R
SPMSTR
0
1
= Reserved
4
CPOL
0
3
2
1
CPHA SPWOM SPE
1
0
0
= Unimplemented
Figure 16-14. SPI Control Register (SPCR)
Bit 0
SPTIE
0
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPRF bit.
The SPRF bit is set when a byte transfers from the shift register to the receive
data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode operation.
Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin between
transmissions. (See Figure 16-5 and Figure 16-7.) To transmit data between
SPI modules, the SPI modules must have identical CPOL values. Reset clears
the CPOL bit.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial clock and
SPI data. (See Figure 16-5 and Figure 16-7.) To transmit data between SPI
modules, the SPI modules must have identical CPHA values. When CPHA = 0,
the SS pin of the slave SPI module must be set to logic 1 between bytes. (See
Figure 16-13.) Reset sets the CPHA bit.
SPWOM — SPI Wired-OR Mode Bit
This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO
so that those pins become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
SPE — SPI Enable
This read/write bit enables the SPI module. Clearing SPE causes a partial reset
of the SPI. (See 16.9 Resetting the SPI.) Reset clears the SPE bit.
1 = SPI module enabled
0 = SPI module disabled
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Serial Peripheral Interface (SPI) Module
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Data Sheet
235