MC68HC908GR16 Datasheet, PDF (155/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
Interrupts
• Receiver overrun bit (OR) — OR is set when the receive shift register shifts
in a new character before the previous character was read from the SCI data
register. The overrun interrupt enable bit, ORIE, enables OR to generate
SCI error CPU interrupt requests. OR is in SCI status register 1. ORIE is in
SCI control register 3.
• Noise flag (NF) — NF is set when the SCI detects noise on incoming data
or break characters, including start, data, and stop bits. The noise error
interrupt enable bit, NEIE, enables NF to generate SCI error CPU interrupt
requests. NF is in SCI status register 1. NEIE is in SCI control register 3.
• Framing error bit (FE) — FE is set when a logic 0 occurs where the receiver
expects a stop bit. The framing error interrupt enable bit, FEIE, enables FE
to generate SCI error CPU interrupt requests. FE is in SCI status register 1.
FEIE is in SCI control register 3.
• Parity error bit (PE) — PE is set when the SCI detects a parity error in
incoming data. The parity error interrupt enable bit, PEIE, enables PE to
generate SCI error CPU interrupt requests. PE is in SCI status register 1.
PEIE is in SCI control register 3.
13.3.2.9 KBD0–KBD7 Pins
A logic 0 on a keyboard interrupt pin latches an external interrupt request.
13.3.2.10 Analog-to-Digital Converter (ADC)
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt
after each ADC conversion. The COCO bit is not used as a conversion complete
flag when interrupts are enabled.
13.3.2.11 Timebase Module (TBM)
The timebase module can interrupt the CPU on a regular basis with a rate defined
by TBR2–TBR0. When the timebase counter chain rolls over, the TBIF flag is set.
If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will
generate a CPU interrupt request.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
13.3.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources.
Table 13-2 summarizes the interrupt sources and the interrupt status register flags
that they set. The interrupt status registers can be useful for debugging.
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Resets and Interrupts
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Data Sheet
155