MC68HC908GR16 Datasheet, PDF (58/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
Table 3-2. ADC Clock Divide Ratio
ADIV2
ADIV1
0
0
0
0
0
1
0
1
1
X⁽¹⁾
1. X = Don’t care
ADIV0
0
1
0
1
X⁽¹⁾
ADC Clock Rate
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
ADICLK — ADC Input Clock Select Bit
ADICLK selects either the bus clock or the oscillator output clock (CGMXCLK)
as the input clock source to generate the internal ADC clock. Reset selects
CGMXCLK as the ADC clock source.
1 = Internal bus clock
0 = Oscillator output clock (CGMXCLK)
The ADC requires a clock rate of approximately 1 MHz for correct operation. If the
selected clock source is not fast enough, the ADC will generate incorrect
conversions. See 20.13 5.0-Volt ADC Characteristics and 20.14 3.3-Volt ADC
Characteristics.
f_CGMXCLK or bus frequency
f_ADIC =
ADIV[2:0]
≅ 1 MHz
MODE1 and MODE0 — Modes of Result Justification Bits
MODE1 and MODE0 select among four modes of operation. The manner in
which the ADC conversion results will be placed in the ADC data registers is
controlled by these modes of operation. Reset returns right-justified mode.
00 = 8-bit truncation mode
01 = Right justified mode
10 = Left justified mode
11 = Left justified signed data mode
Data Sheet
58
Analog-to-Digital Converter (ADC)
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Go to: www.freescale.com
MC68HC908GR16 — Rev. 1.0
MOTOROLA