MC68HC908GR16 Datasheet, PDF (217/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI) Module
Pin Name Conventions
16.3 Pin Name Conventions
The text that follows describes the SPI. The SPI I/O pin names are SS (slave
select), SPSCK (SPI serial clock), CGND (clock ground), MOSI (master out slave
in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel
I/O ports.
The full names of the SPI I/O pins are shown in Table 16-1. The generic pin names
appear in the text that follows.
.
Table 16-1. Pin Name Conventions
SPI Generic
Pin Names:
Full SPI
Pin Names:
SPI
MISO
PTD1/MISO
MOSI
PTD2/MOSI
SS
PTD0/SS
SPSCK
PTD3/SPSCK
CGND
V_SS
16.4 Functional Description
Figure 16-2 summarizes the SPI I/O registers and Figure 16-3 shows the structure
of the SPI module.
The SPI module allows full-duplex, synchronous, serial communication between
the MCU and peripheral devices, including other MCUs. Software can poll the SPI
status flags or SPI operation can be interrupt driven.
If a port bit is configured for input, then an internal pullup device may be enabled
for that port bit. See 12.4.3 Port C Input Pullup Enable Register.
The following paragraphs describe the operation of the SPI module.
Addr.
$0010
$0011
$0012
Register Name
SPI Control Register ^Read:
(SPCR) Write:
See page 235. _Reset:
SPI Status and Control ^Read:
Register (SPSCR) Write:
See page 236.
Reset:
Read:
SPI Data Register
(SPDR) Write:
See page 238. _Reset:
Bit 7
SPRIE
0
SPRF
0
R7
T7
R
6
5
R
SPMSTR
0
ERRIE
1
OVRF
0
0
R6
R5
T6
T5
= Reserved
4
3
2
CPOL CPHA SPWOM
0
MODF
1
SPTE
0
MODFEN
0
1
0
R4
R3
R2
T4
T3
T2
Unaffected by reset
= Unimplemented
Figure 16-2. SPI I/O Register Summary
1
SPE
0
SPR1
0
R1
T1
Bit 0
SPTIE
0
SPR0
0
R0
T0
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Serial Peripheral Interface (SPI) Module
For More Information On This Product,
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Data Sheet
217