MC68HC908GR16 Datasheet, PDF (51/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
Functional Description
NOTE:
Left justified sign data mode is similar to left justified mode with one exception. The
MSB of the 10-bit result, AD9 located in ADRH, is complemented. This mode of
operation is useful when a result, represented as a signed magnitude from
mid-scale, is needed. Finally, 8-bit truncation mode will place the eight MSBs in the
ADC data register low, ADRL. The two LSBs are dropped. This mode of operation
is used when compatibility with 8-bit ADC designs are required. No interlocking
between ADRH and ADRL is present.
Quantization error is affected when only the most significant eight bits are used as
a result. See Figure 3-3.
8-BIT 10-BIT
RESULT RESULT
003
00B
IDEAL 8-BIT CHARACTERISTIC
WITH QUANTIZATION = ±1/2
10-BIT TRUNCATED
TO 8-BIT RESULT
00A
IDEAL 10-BIT CHARACTERISTIC
009 WITH QUANTIZATION = ±1/2
002
008
007
006
005
001
004
003
002
WHEN TRUNCATION IS USED,
ERROR FROM IDEAL 8-BIT = 3/8 LSB
DUE TO NON-IDEAL QUANTIZATION.
001
000
000
1/2
2 1/2
4 1/2
6 1/2
8 1/2
INPUT VOLTAGE
1 1/2
3 1/2
5 1/2
7 1/2
9 1/2
REPRESENTED AS 10-BIT
INPUT VOLTAGE
1/2
1 1/2
2 1/2
REPRESENTED AS 8-BIT
Figure 3-3. Bit Truncation Mode Error
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Analog-to-Digital Converter (ADC)
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Data Sheet
51