MC68HC908GR16 Datasheet, PDF (61/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Functional Description
4.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external
crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output.
The SIMOSCEN signal from the system integration module (SIM) or the
OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate
equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK,
the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for
operation. The duty cycle of CGMXCLK is not guaranteed to be 50% and depends
on external factors, including the crystal and related external components. An
externally generated clock also can feed the OSC1 pin of the crystal oscillator
circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.
4.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or
tracking mode, depending on the accuracy of the output frequency. The PLL can
change between acquisition and tracking modes either automatically or manually.
4.3.3 PLL Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Reference divider
• Frequency prescaler
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
The operating range of the VCO is programmable for a wide range of frequencies
and for maximum immunity to external noise, including supply and CGM/XFC
noise. The VCO frequency is bound to a range from roughly one-half to twice the
center-of-range frequency, f_VRS. Modulating the voltage on the CGM/XFC pin
changes the frequency within this range. By design, f_VRS is equal to the nominal
center-of-range frequency, f_NOM, (38.4 kHz) times a linear factor, L, and a
power-of-two factor, E, or (L × 2^E)f_NOM.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f_RCLK, and is fed to the PLL through a
programmable modulo reference divider, which divides f_RCLK by a factor, R. The
divider’s output is the final reference clock, CGMRDV, running at a frequency,
f_RDV = f_RCLK/R. With an external crystal (30 kHz–100 kHz), always set R = 1 for
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Clock Generator Module (CGM)
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Data Sheet
61