MC68HC908GR16 Datasheet, PDF (126/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
or V_DD decreases to approximately 0 V which will re-trigger the power-on reset and
reset the trip point to 3-V operation.
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register
(CONFIG1). See Figure 5-2. Configuration Register 1 (CONFIG1) for details of
the LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in reset
until V_DD rises above a voltage, V_TRIPR, which causes the MCU to exit reset. See
15.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the
SIM and the LVI. The output of the comparator controls the state of the LVIOUT
flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to
external peripheral devices.
V_DD
LVIPWRD
FROM CONFIG
STOP INSTRUCTION
FROM CONFIG1
LVIRSTD
LVISTOP
FROM CONFIG1
LOW V_DD
DETECTOR
V_DD > LVI_Trip = 0
V_DD £ LVI_Trip = 1
LVI5OR3
FROM CONFIG1
LVIOUT
Figure 11-1. LVI Module Block Diagram
LVI RESET
Addr. Register Name
Bit 7
6
5
4
3
2
1
Bit 0
LVI Status Register ^{Read: LVIOUT}
0
0
0
0
0
0
0
$FE0C
(LVISR) Write:
See page 127. _Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-2. LVI I/O Register Summary
Data Sheet
126
Low-Voltage Inhibit (LVI)
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MC68HC908GR16 — Rev. 1.0
MOTOROLA