MC68HC908GR16 Datasheet, PDF (169/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Enhanced Serial Communications Interface (ESCI) Module
Functional Description
14.4.3.2 Character Reception
During an ESCI reception, the receive shift register shifts characters in from the
RxD pin. The ESCI data register (SCDR) is the read-only buffer between the
internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of
the character transfers to the SCDR. The ESCI receiver full bit, SCRF, in ESCI
status register 1 (SCS1) becomes set, indicating that the received byte can be
read. If the ESCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF
bit generates a receiver CPU interrupt request.
14.4.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal
signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch,
the RT clock is resynchronized at these times (see Figure 14-7):
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0 (after the
majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1
and the majority of the next RT8, RT9, and RT10 samples returns a valid
logic 0)
To locate the start bit, data recovery logic does an asynchronous search for a
logic 0 preceded by three logic 1s. When the falling edge of a possible start bit
occurs, the RT clock begins to count to 16.
START BIT
LSB
RxD
SAMPLES
START BIT
START BIT
DATA
QUALIFICATION VERIFICATION SAMPLING
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
Figure 14-7. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3,
RT5, and RT7. Table 14-2 summarizes the results of the start bit verification
samples.
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Enhanced Serial Communications Interface (ESCI) Module
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Data Sheet
169