MC68HC908GR16 Datasheet, PDF (223/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI) Module
Transmission Formats
data register of the slave must be loaded with transmit data before the first edge of
SPSCK. Any data written after the first edge is stored in the transmit data register
and transferred to the shift register after the current transmission.
SPSCK CYCLE #
FOR REFERENCE
SPSCK; CPOL = 0
1
2
3
4
5
6
7
8
SPSCK; CPOL =1
MOSI
FROM MASTER
MISO
FROM SLAVE
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
SS; TO SLAVE
CAPTURE STROBE
Figure 16-7. Transmission Format (CPHA = 1)
LSB
LSB
16.5.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts
a transmission. CPHA has no effect on the delay to the start of the transmission,
but it does affect the initial state of the SPSCK signal. When CPHA = 0, the SPSCK
signal remains inactive for the first half of the first SPSCK cycle. When CPHA = 1,
the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to
its active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from
the write to SPDR and the start of the SPI transmission. (See Figure 16-8.) The
internal SPI clock in the master is a free-running derivative of the internal MCU
clock. To conserve power, it is enabled only when both the SPE and SPMSTR bits
are set. SPSCK edges occur halfway through the low time of the internal MCU
clock. Since the SPI clock is free-running, it is uncertain where the write to the
SPDR occurs relative to the slower SPSCK. This uncertainty causes the variation
in the initiation delay shown in Figure 16-8. This delay is no longer than a single
SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight
MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles
for DIV128.
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Serial Peripheral Interface (SPI) Module
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Data Sheet
223