MC68HC908GR16 Datasheet, PDF (83/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Configuration Register (CONFIG)
Functional Description
NOTE:
NOTE:
COPRS — COP Rate Select Bit
COPD selects the COP timeout period. Reset clears COPRS. See Section 6.
Computer Operating Properly (COP) Module
1 = COP timeout period = 2¹³ – 2⁴ COPCLK cycles
0 = COP timeout period = 2¹⁸ – 2⁴ COPCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to
operate during stop mode. Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. See Section 11.
Low-Voltage Inhibit (LVI).
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. See Section 11. Low-Voltage Inhibit
(LVI).
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module (see Section
11. Low-Voltage Inhibit (LVI)). The voltage mode selected for the LVI should
match the operating V_DD (see Section 20. Electrical Specifications) for the
LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5-V mode
0 = LVI operates in 3-V mode
The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets will leave
this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles
instead of a 4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLCK cycles
Exiting stop mode by an LVI reset will result in the long stop recovery.
If the system clock source selected is the internal oscillator or the external
crystal and the OSCENINSTOP configuration bit is not set, the oscillator will be
disabled during stop mode. The short stop recovery does not provide enough
time for oscillator stabilization and for this reason the SSREC bit should not
be set.
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Configuration Register (CONFIG)
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Data Sheet
83