MC68HC908GR16 Datasheet, PDF (267/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
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Break Module (BRK)
19.2.2.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to
disable the COP while the MCU is in a state of break interrupt with monitor mode.
Address: $FE02
Bit 7
6
5
4
3
2
1
Read: 0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 19-6. Break Auxiliary Register (BRKAR)
Bit 0
BDCOP
0
BDCOP — Break Disable COP Bit
This read/write bit disables the COP during a break interrupt. Reset clears the
BDCOP bit.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt.
19.2.2.4 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an
exit from wait mode. This register is only used in emulation mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
R
R
R
R
R
R
Write:
Note⁽¹⁾
Reset:
0
R = Reserved
1. Writing a logic 0 clears SBSW.
Figure 19-7. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait mode after
exiting from a break interrupt. Clear SBSW by writing a logic 0 to it. Reset clears
SBSW.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can modify the
return address on the stack by subtracting one from it.
MC68HC908GR16 — Rev. 1.0
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Data Sheet
267