MC68HC908GR16 Datasheet, PDF (250/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
18.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The prescaler
generates seven clock rates from the internal bus clock. The prescaler select bits,
PS[2:0], in the TIM status and control register select the TIM clock source.
18.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external
event occurs. When an active edge occurs on the pin of an input capture channel,
the TIM latches the contents of the TIM counter into the TIM channel registers,
TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures
can generate TIM CPU interrupt requests.
18.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a
programmable polarity, duration, and frequency. When the counter reaches the
value in the registers of an output compare channel, the TIM can set, clear, or
toggle the channel pin. Output compares can generate TIM CPU interrupt
requests.
18.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as
described in 18.4.3 Output Compare. The pulses are unbuffered because
changing the output compare value requires writing the new value over the old
value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare
value could cause incorrect operation for up to two counter overflow periods. For
example, writing a new value before the counter reaches the old value but after the
counter reaches the new value prevents any compare during that counter overflow
period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new
value before it is written.
Use the following methods to synchronize unbuffered changes in the output
compare value on channel x:
• When changing to a smaller value, enable channel x output compare
interrupts and write the new value in the output compare interrupt routine.
The output compare interrupt occurs at the end of the current output
compare pulse. The interrupt routine has until the end of the counter
overflow period to write the new value.
• When changing to a larger output compare value, enable TIM overflow
interrupts and write the new value in the TIM overflow interrupt routine. The
TIM overflow interrupt occurs at the end of the current counter overflow
Data Sheet
250
Timer Interface Module (TIM)
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MC68HC908GR16 — Rev. 1.0
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