MC68HC908GR16 Datasheet, PDF (231/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI) Module
Low-Power Modes
These items are reset only by a system reset:
• All control bits in the SPCR register
• All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0)
• The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE between
transmissions without having to set all control bits again when SPE is set back high
for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still service these
interrupts after the SPI has been disabled. The user can disable the SPI by
writing 0 to the SPE bit. The SPI can also be disabled by a mode fault occurring in
an SPI that was configured as a master with the MODFEN bit set.
16.10 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby
modes.
16.10.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction. In wait
mode the SPI module registers are not accessible by the CPU. Any enabled CPU
interrupt request from the SPI module can bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF bit to
generate CPU interrupt requests by setting the error interrupt enable bit (ERRIE).
See 16.8 Interrupts.
16.10.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions. SPI operation resumes after an
external interrupt. If stop mode is exited by reset, any transfer in progress is
aborted, and the SPI is reset.
16.11 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules
can be cleared during the break state. The BCFE bit in the SIM break flag control
register (SBFCR) enables software to clear status bits during the break state. See
Section 15. System Integration Module (SIM).
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Serial Peripheral Interface (SPI) Module
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Data Sheet
231