MC68HC908GR16 Datasheet, PDF (275/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Development Support
Monitor ROM (MON)
19.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ)
mark/space data format. Transmit and receive baud rates must be identical.
START
BIT BIT 0
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
NEXT
START
BIT 6 BIT 7 STOP BIT
BIT
Figure 19-13. Monitor Data Format
19.3.1.5 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor
receives a break signal, it drives the PTA0 pin high for the duration of two bits and
then echoes back the break signal.
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
01234567
01234567
Figure 19-14. Break Transaction
19.3.1.6 Baud Rate
The communication baud rate is controlled by the crystal frequency or external
clock and the state of the PTB4 pin (when IRQ is set to V_TST) upon entry into
monitor mode. If monitor mode was entered with V_DD on IRQ and the reset vector
blank, then the baud rate is independent of PTB4.
Table 19-1 also lists external frequencies required to achieve a standard baud rate
of 9600 bps. The effective baud rate is the bus frequency divided by 256. If using
a crystal as the clock source, be aware of the upper frequency limit that the internal
clock module can handle. See 20.7 5.0-Volt Control Timing or 20.8 3.3-Volt
Control Timing for this limit.
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Development Support
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Data Sheet
275