MC68HC908GR16 Datasheet, PDF (240/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timebase Module (TBM)
17.4 Interrupts
The timebase module can periodically interrupt the CPU with a rate defined by the
selected TBMCLK and the select bits TBR2–TBR0. When the timebase counter
chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt request.
TBMCLKSEL
FROM CONFIG2
CGMXCLK
FROM CGM MODULE
DIVIDE BY 128
PRESCALER
0
TBMCLK
1
÷2 ÷2 ÷2
÷2
÷2
÷2
÷2
TBON
TBMINT
÷2 ÷2 ÷2 ÷2
÷2 ÷2
÷2 ÷2
TBIF
TBIE
000
R
001
010
011
100
101
110
111
NOTE:
Figure 17-1. Timebase Block Diagram
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
Data Sheet
240
Timebase Module (TBM)
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MC68HC908GR16 — Rev. 1.0
MOTOROLA