MC68HC908GR16 Datasheet, PDF (174/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Enhanced Serial Communications Interface (ESCI) Module
• Noise flag (NF) — The NF bit is set when the ESCI detects noise on
incoming data or break characters, including start, data, and stop bits. The
noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate ESCI
error CPU interrupt requests.
• Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where
the receiver expects a stop bit. The framing error interrupt enable bit, FEIE,
in SCC3 enables FE to generate ESCI error CPU interrupt requests.
• Parity error (PE) — The PE bit in SCS1 is set when the ESCI detects a parity
error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3
enables PE to generate ESCI error CPU interrupt requests.
14.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby
modes.
14.5.1 Wait Mode
The ESCI module remains active in wait mode. Any enabled CPU interrupt request
from the ESCI module can bring the MCU out of wait mode.
If ESCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT instruction.
14.5.2 Stop Mode
The ESCI module is inactive in stop mode. The STOP instruction does not affect
ESCI register states. ESCI module operation resumes after the MCU exits stop
mode.
Because the internal clock is inactive during stop mode, entering stop mode during
an ESCI transmission or reception results in invalid data.
14.6 ESCI During Break Module Interrupts
The BCFE bit in the break flag control register (SBFCR) enables software to clear
status bits during the break state. See Section 19. Development Support.
To allow software to clear status bits during a break interrupt, write a logic 1 to the
BCFE bit. If a status bit is cleared during the break state, it remains cleared when
the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With
BCFE at logic 0 (its default state), software can read and write I/O registers during
the break state without affecting status bits. Some status bits have a two-step
read/write clearing procedure. If software does the first step on such a bit before
Data Sheet
174
MC68HC908GR16 — Rev. 1.0
Enhanced Serial Communications Interface (ESCI) Module
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