MC68HC908GR16 Datasheet, PDF (55/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
I/O Registers
The voltage levels supplied from internal reference nodes, as specified in
Table 3-1, are used to verify the operation of the ADC converter both in production
test and for user applications.
Table 3-1. Mux Channel Select⁽¹⁾
ADCH4
0
0
0
0
0
0
0
0
0
↓
1
1
1
1
ADCH3
0
0
0
0
0
0
0
0
1
↓
1
1
1
1
ADCH2
0
0
0
0
1
1
1
1
0
↓
1
1
1
1
ADCH1
0
0
1
1
0
0
1
1
0
↓
0
0
1
1
ADCH0
0
1
0
1
0
1
0
1
0
↓
0
1
0
1
Input Select
PTB0/AD0
PTB1/AD1
PTB2/AD2
PTB3/AD3
PTB4/AD4
PTB5/AD5
PTB6/AD6
PTB7/AD7
Unused
V_REFH
V_REFL
ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be unknown or
reserved.
3.8.2 ADC Data Register High and Data Register Low
3.8.2.1 Left Justified Mode
In left justified mode, the ADRH register holds the eight MSBs of the 10-bit result.
The only difference from left justified mode is that the AD9 is complemented. The
ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0.
ADRH and ADRL are updated each time an ADC single channel conversion
completes. Reading ADRH latches the contents of ADRL until ADRL is read. All
subsequent results will be lost until the ADRH and ADRL reads are completed.
Address: $003D
ADRH
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
Write:
Reset:
Unaffected by reset
Address: $003E
ADRL
Read: AD1
AD0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Unaffected by reset
Figure 3-5. ADC Data Register High (ADRH) and Low (ADRL)
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Analog-to-Digital Converter (ADC)
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
55