MC68HC908GR16 Datasheet, PDF (166/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Enhanced Serial Communications Interface (ESCI) Module
14.4.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift
register with a break character. For TXINV = 0 (output not inverted), a transmitted
break character contains all logic 0s and has no start, stop, or parity bit. Break
character length depends on the M bit in SCC1 and the LINR bits in SCBR. As long
as SBK is at logic 1, transmitter logic continuously loads break characters into the
transmit shift register. After software clears the SBK bit, the shift register finishes
transmitting the last break character and then transmits at least one logic 1. The
automatic logic 1 at the end of a break character guarantees the recognition of the
start bit of the next character.
When LINR is cleared in SCBR, the ESCI recognizes a break character when a
start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit
should be, resulting in a total of 10 or 11 consecutive logic 0 data bits. When LINR
is set in SCBR, the ESCI recognizes a break character when a start bit is followed
by 9 or 10 logic 0 data bits and a logic 0 where the stop bit should be, resulting in
a total of 11 or 12 consecutive logic 0 data bits.
Receiving a break character has these effects on ESCI registers:
• Sets the framing error bit (FE) in SCS1
• Sets the ESCI receiver full bit (SCRF) in SCS1
• Clears the ESCI data register (SCDR)
• Clears the R8 bit in SCC3
• Sets the break flag bit (BKF) in SCS2
• May set the overrun (OR), noise flag (NF), parity error (PE),
or reception in progress flag (RPF) bits
14.4.2.4 Idle Characters
For TXINV = 0 (output not inverted), a transmitted idle character contains all logic
1s and has no start, stop, or parity bit. Idle character length depends on the M bit
in SCC1. The preamble is a synchronizing idle character that begins every
transmission.
If the TE bit is cleared during a transmission, the TxD pin becomes idle after
completion of the transmission in progress. Clearing and then setting the TE bit
during a transmission queues an idle character to be sent after the character
currently being transmitted.
NOTE:
When a break sequence is followed immediately by an idle character, this SCI
design exhibits a condition in which the break character length is reduced by one
half bit time. In this instance, the break sequence will consist of a valid start bit,
eight or nine data bits (as defined by the M bit in SCC1) of logic 0 and one half data
bit length of logic 0 in the stop bit position followed immediately by the idle
character. To ensure a break character of the proper length is transmitted, always
queue up a byte of data to be transmitted while the final break sequence is in
progress.
Data Sheet
166
MC68HC908GR16 — Rev. 1.0
Enhanced Serial Communications Interface (ESCI) Module
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