MC68HC908GR16 Datasheet, PDF (226/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI) Module
16.7 Error Conditions
The following flags signal SPI error conditions:
• Overflow (OVRF) — Failing to read the SPI data register before the next full
byte enters the shift register sets the OVRF bit. The new byte does not
transfer to the receive data register, and the unread byte still can be read.
OVRF is in the SPI status and control register.
• Mode fault error (MODF) — The MODF bit indicates that the voltage on the
slave select pin (SS) is inconsistent with the mode of the SPI. MODF is in
the SPI status and control register.
16.7.1 Overflow Error
The overflow flag (OVRF) becomes set if the receive data register still has unread
data from a previous transmission when the capture strobe of bit 1 of the next
transmission occurs. The bit 1 capture strobe occurs in the middle of SPSCK
cycle 7 (see Figure 16-5 and Figure 16-7.) If an overflow occurs, all data received
after the overflow and before the OVRF bit is cleared does not transfer to the
receive data register and does not set the SPI receiver full bit (SPRF). The unread
data that transferred to the receive data register before the overflow occurred can
still be read. Therefore, an overflow error always indicates the loss of data. Clear
the overflow flag by reading the SPI status and control register and then reading
the SPI data register.
OVRF generates a receiver/error CPU interrupt request if the error interrupt enable
bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same
CPU interrupt vector (see Figure 16-12.) It is not possible to enable MODF or
OVRF individually to generate a receiver/error CPU interrupt request. However,
leaving MODFEN low prevents MODF from being set.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an
overflow condition. Figure 16-10 shows how it is possible to miss an overflow.
The first part of Figure 16-10 shows how it is possible to read the SPSCR and
SPDR to clear the SPRF without problems. However, as illustrated by the second
transmission example, the OVRF bit can be set in between the time that SPSCR
and SPDR are read.
In this case, an overflow can be missed easily. Since no more SPRF interrupts can
be generated until this OVRF is serviced, it is not obvious that bytes are being lost
as more transmissions are completed. To prevent this, either enable the OVRF
interrupt or do another read of the SPSCR following the read of the SPDR. This
ensures that the OVRF was not set before the SPRF was cleared and that future
transmissions can set the SPRF bit. Figure 16-11 illustrates this process.
Generally, to avoid this second SPSCR read, enable the OVRF to the CPU by
setting the ERRIE bit.
Data Sheet
226
Serial Peripheral Interface (SPI) Module
For More Information On This Product,
Go to: www.freescale.com
MC68HC908GR16 — Rev. 1.0
MOTOROLA