MC68HC908GR16 Datasheet, PDF (221/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI) Module
Transmission Formats
16.5.1 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SPSCK) phase and
polarity using two bits in the SPI control register (SPCR). The clock polarity is
specified by the CPOL control bit, which selects an active high or low clock and has
no significant effect on the transmission format.
The clock phase (CPHA) control bit selects one of two fundamentally different
transmission formats. The clock phase and polarity should be identical for the
master SPI device and the communicating slave device. In some cases, the phase
and polarity are changed between transmissions to allow a master device to
communicate with peripheral slaves having different requirements.
NOTE: Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing the SPI
enable bit (SPE).
16.5.2 Transmission Format When CPHA = 0
Figure 16-5 shows an SPI transmission in which CPHA is logic 0. The figure should
not be used as a replacement for data sheet parametric information.
Two waveforms are shown for SPSCK: one for CPOL = 0 and another for
CPOL = 1. The diagram may be interpreted as a master or slave timing diagram
since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave
in (MOSI) pins are directly connected between the master and the slave. The MISO
signal is the output from the slave, and the MOSI signal is the output from the
master. The SS line is the slave select input to the slave. The slave SPI drives its
MISO output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not shown but is
assumed to be inactive. The SS pin of the master must be high or must be
reconfigured as general-purpose I/O not affecting the SPI. (See 16.7.2 Mode Fault
Error.) When CPHA = 0, the first SPSCK edge is the MSB capture strobe.
Therefore, the slave must begin driving its data before the first SPSCK edge, and
a falling edge on the SS pin is used to start the slave data transmission. The slave’s
SS pin must be toggled back to high and then low again between each byte
transmitted as shown in Figure 16-6.
When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the
transmission. This causes the SPI to leave its idle state and begin driving the MISO
pin with the MSB of its data. Once the transmission begins, no new data is allowed
into the shift register from the transmit data register. Therefore, the SPI data
register of the slave must be loaded with transmit data before the falling edge of
SS. Any data written after the falling edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Serial Peripheral Interface (SPI) Module
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Data Sheet
221