MC68HC908GR16 Datasheet, PDF (147/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
Resets
13.2.3.3 Low-Voltage Inhibit (LVI) Reset
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in the power
supply voltage to the LVI_TRIPF voltage.
An LVI reset:
• Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles after the power supply voltage
rises to the LVI_TRIPR voltage
• Drives the RST pin low for as long as V_DD is below the LVI_TRIPR voltage and
during the oscillator stabilization delay
• Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization
delay
• Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles
after the oscillator stabilization delay
• Sets the LVI bit in the SIM reset status register
13.2.3.4 Illegal Opcode Reset
An illegal opcode reset is an internal reset caused by an opcode that is not in the
instruction set. An illegal opcode reset sets the ILOP bit in the SIM reset status
register.
If the stop enable bit, STOP, in the mask option register is a logic 0, the STOP
instruction causes an illegal opcode reset.
13.2.3.5 Illegal Address Reset
An illegal address reset is an internal reset caused by opcode fetch from an
unmapped address. An illegal address reset sets the ILAD bit in the SIM reset
status register.
A data fetch from an unmapped address does not generate a reset.
13.2.4 System Integration Module (SIM) Reset Status Register
This read-only register contains flags to show reset sources. All flag bits are
automatically cleared following a read of the register. Reset service can read the
SIM reset status register to clear the register after power-on reset and to determine
the source of any subsequent reset.
The register is initialized on power-up as shown with the POR bit set and all other
bits cleared. During a POR or any other internal reset, the RST pin is pulled low.
After the pin is released, it will be sampled 32 CGMXCLK cycles later. If the pin is
not above a V_IH at that time, then the PIN bit in the SRSR may be set in addition to
whatever other bits are set.
NOTE: Only a read of the SIM reset status register clears all reset flags. After multiple
resets from different sources without reading the register, multiple flags remain set.
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Resets and Interrupts
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Data Sheet
147