MC68HC908GR16 Datasheet, PDF (265/310 Pages) Motorola, Inc – Microcontrollers

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Break Module (BRK)
19.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits
can be cleared during the break state. The BCFE bit in the break flag control
register (BFCR) enables software to clear status bits during the break state. See
15.7.3 Break Flag Control Register and the Break Interrupts subsection for
each module.
19.2.1.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor
mode)
The break interrupt begins after completion of the CPU instruction in progress. If
the break address register match occurs on the last cycle of a CPU instruction, the
break interrupt begins immediately.
19.2.1.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
19.2.1.4 COP During Break Interrupts
The COP is disabled during a break interrupt with monitor mode when BDCOP bit
is set in break auxiliary register (BRKAR).
19.2.2 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• Break status register (BSR)
• Break flag control register (BFCR)
MC68HC908GR16 — Rev. 1.0
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Data Sheet
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