MC68HC908GR16 Datasheet, PDF (232/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI) Module
To allow software to clear status bits during a break interrupt, write a logic 1 to the
BCFE bit. If a status bit is cleared during the break state, it remains cleared when
the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With
BCFE at logic 0 (its default state), software can read and write I/O registers during
the break state without affecting status bits. Some status bits have a 2-step
read/write clearing procedure. If software does the first step on such a bit before
the break, the bit cannot change during the break state as long as BCFE is at
logic 0. After the break, doing the second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a
write to the transmit data register in break mode does not initiate a transmission nor
is this data transferred into the shift register. Therefore, a write to the SPDR in
break mode with the BCFE bit cleared has no effect.
16.12 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel I/O port.
They are:
• MISO — Data received
• MOSI — Data transmitted
• SPSCK — Serial clock
• SS — Slave select
• CGND — Clock ground (internally connected to V_SS)
The SPI has limited inter-integrated circuit (I²C) capability (requiring software
support) as a master in a single-master environment. To communicate with I²C
peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI
control register is set. In I²C communication, the MOSI and MISO pins are
connected to a bidirectional pin from the I²C peripheral and through a pullup
resistor to V_DD.
16.12.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full duplex
operation, the MISO pin of the master SPI module is connected to the MISO pin of
the slave SPI module. The master SPI simultaneously receives data on its MISO
pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is configured as
a slave. The SPI is configured as a slave when its SPMSTR bit is logic 0 and its SS
pin is at logic 0. To support a multiple-slave system, a logic 1 on the SS pin puts
the MISO pin in a high-impedance state.
When enabled, the SPI controls data direction of the MISO pin regardless of the
state of the data direction register of the shared I/O port.
Data Sheet
232
Serial Peripheral Interface (SPI) Module
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Go to: www.freescale.com
MC68HC908GR16 — Rev. 1.0
MOTOROLA