MC68HC908GR16 Datasheet, PDF (201/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
System Integration Module (SIM)
Reset and System Initialization
IRST
RST
CGMXCLK
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
IAB
Figure 15-6. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
VECTOR HIGH
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
MODRST
INTERNAL RESET
Figure 15-7. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals and other
chips within a system built around the MCU.
15.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR)
generates a pulse to indicate that power-on has occurred. The external reset pin
(RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles.
Thirty-two CGMXCLK cycles later, the CPU and memories are released from reset
to allow the reset vector sequence to occur.
At power-on, these events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables CGMOUT.
• Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set and all other bits
in the register are cleared.
MC68HC908GR16 — Rev. 1.0
MOTOROLA
System Integration Module (SIM)
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
201