MC68HC908GR16 Datasheet, PDF (35/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Memory
Input/Output (I/O) Section
Addr.
Register Name
$003C
ADC Status and Control ^Read:
Register (ADSCR) Write:
See page 54. _Reset:
$003D
ADC Data High Register ^Read:
(ADRH) Write:
See page 55. _Reset:
$003E
ADC Data Low Register ^Read:
(ADRL) Write:
See page 55. _Reset:
$003F
ADC Clock Register ^Read:
(ADCLK) Write:
See page 57. _Reset:
$FE00
Break Status Register ^Read:
(BSR) Write:
See page 267. _Reset:
2. Writing a logic 0 clears SBSW.
$FE01
SIM Reset Status Register ^Read:
(SRSR) Write:
See page 213. _POR:
$FE02
Break Auxiliary Register ^Read:
(BRKAR) Write:
See page 267. _Reset:
$FE03
Break Flag Control ^Read:
Register (BFCR) Write:
See page 268. _Reset:
$FE04
Interrupt Status Register 1 ^Read:
(INT1) Write:
See page 156. _Reset:
$FE05
Interrupt Status Register 2 ^Read:
(INT2) Write:
See page 157. _Reset:
$FE06
Interrupt Status Register 3 ^Read:
(INT3) Write:
See page 157. _Reset:
Bit 7
COCO
0
0
AD7
ADIV2
0
R
0
POR
1
Bit 7
0
BCFE
0
IF6
R
0
IF14
R
0
0
R
0
6
AIEN
0
0
AD6
ADIV1
0
R
0
PIN
0
6
0
R
0
IF5
R
0
IF13
R
0
0
R
0
5
ADCO
0
0
4
ADCH4
1
0
3
ADCH3
1
0
2
ADCH2
1
0
1
ADCH1
1
AD9
Bit 0
ADCH0
1
AD9
Unaffected by reset
AD5
AD4
A3
AD2
AD1
AD0
Unaffected by reset
0
ADIV0 ADICLK MODE1 MODE0
R
0
0
0
1
0
0
SBSW
R
R
R
R
R
(Note 2)
0
0
0
0
0
0
COP
ILOP
ILAD MODRST LVI
0
0
0
0
0
0
0
5
4
3
2
1
Bit 0
0
0
0
0
0
0
R
R
R
R
R
R
0
0
0
0
0
0
IF4
IF3
IF2
IF1
0
0
R
R
R
R
R
R
0
0
0
0
0
0
IF12
IF11
IF10
IF9
IF8
IF7
R
R
R
R
R
R
0
0
0
0
0
0
IF20
IF19
IF18
IF17
IF16
IF15
R
R
R
R
R
R
0
0
0
0
0
0
= Unimplemented
R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 7)
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Memory
For More Information On This Product,
Go to: www.freescale.com
Data Sheet
35