MC68HC908GR16 Datasheet, PDF (87/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Computer Operating Properly (COP) Module
COP Control Register
6.3.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
6.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A
reset vector fetch clears the COP prescaler.
6.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register. See Section 5. Configuration Register (CONFIG).
6.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the
configuration register. See Section 5. Configuration Register (CONFIG).
6.4 COP Control Register
The COP control register (COPCTL) is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and starts a new
timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: $FFFF
Bit 7
6
Read:
Write:
Reset:
5
4
3
2
Low byte of reset vector
Clear COP counter
Unaffected by reset
1
Bit 0
Figure 6-2. COP Control Register (COPCTL)
6.5 Interrupts
The COP does not generate central processor unit (CPU) interrupt requests.
6.6 Monitor Mode
When monitor mode is entered with V_TST on the IRQ pin, the COP is disabled as
long as V_TST remains on the IRQ pin or the RST pin. When monitor mode is
entered by having blank reset vectors and not having V_TST on the IRQ pin, the COP
is automatically disabled until a POR occurs.
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Computer Operating Properly (COP) Module
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Data Sheet
87